gra2001-03

Shortest paths and network flow algorithms for Electrostatic Discharge analysis

by:
Robert B. Gramacy

ABSTRACT

Designers of integrated circuits have always been concerned about the damaging effects of ESD (Electrostatic Discharge). However, as their designs become increasingly more complex, the problem of analyzing the schemes they develop to protect against ESD is quickly becoming too difficult perform manually. Current VLSI (Very Large Scale Integration) designs exceed one hundred bondpads, through which the device communicates with the outside environment, and through which harmful amounts of current might enter the chip. A protection scheme for a complex device such as this might require a network of thousands of non-trivial connections between the bondpads to keep harmful amounts of current from the chip's delicate core. In order to measure the robustness of a protection scheme designers would like to be able to take resistance measurements between bondpad pairs. On such large designs, this can be a monumental task. In this paper we focus on two things: the automation of strategies previously performed manually, and an in-depth development of (newer) more accurate techniques provided by network flow algorithms, each for gauging the degree of protection afforded by ESD Protection Schemes. The underlying algorithms we will discuss for automating this ESD Analysis are well understood. However, their application, and the introduction of more advanced simulation techniques make this discussion original. We would like to develop a tool which not only accurately models the protection scheme against an ESD event, but also helps to pinpoint its weaknesses. In many cases it is not obvious that the techniques we suggest can be applied or adapted to the simulation of electrical devices and networks. It is also interesting that such techniques make no direct use of Kirchoff's Voltage or Current Laws (KVL/KCL) yet still produce meaningful and accurate results. This document is intended to summarize standard techniques for analysis of ESD protection schemes, as well as to introduce some clever variations on more complicated algorithms whose intent is to generate more meaningful results never before feasible manually.

BIBTEX

@UndergradThesis{gra2001:thesis,       Author = {Robert B. Gramacy},       School = {University of Californina},       Address = {Santa Cruz, CA 95064},       Title = {Shortest paths and network flow algorithms for Electrostatic Discharge analysis},       Month = {June},       Year = {2001},       Url = {http://www.ams.ucsc.edu/~rbgramacy/papers/gra2001-03.pdf}       }

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